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راجہ طاہر

راجہ طاہر

ایک پیارا بہادر مارشل لاء کے خلاف جدوجہد کا ساتھی مزاحمتی تحریک کا ایک کردار راجہ طاہر ہم سے بچھڑ گیا ۔پاکستان پیپلز پارٹی کے بانی ارکان میں سے پارٹی قیادت سے گلے شکوے ناراضگی مگر مرتے دم تک پاکستان پیپلز پارٹی کا ساتھ نہ چھوڑا ڈھیری حسن آباد میں سب سے اونچا پاکستان پیپلز پارٹی کا پرچم ان کے گھر ہی لگا نظر آتا ۔گھر میں داخل ہو تو چیئر مین بھٹو شہید کی پرانی تصاویر کے علاوہ کارل مارکس ،لینن ،سٹالن ،چوئی این لائی ،مائوزے تنگ کی کپڑے پر بنی تصاویر خوبصورت فریمز میں لگی نظر آتیں ۔پنجاب یونیورسٹی پیپلز سٹوڈنٹس فیڈریشن PSFکا سرخا راجہ طاہر جسے دیکھ کر اسلا می جمعیت طلبہ والے رستہ بد ل لیتے تھے چیئر مین بھٹو شہید ،محترمہ بے نظیر بھٹو شہیداور میر مرتضی بھٹو شہید اور شاہ نواز بھٹو شہید کے ساتھی گرفتار ہوئے تو جنگ اخبار میں چار کالمی سرخی شاہی قلعہ لاہور منتقل ہوا تو ان کی ماں لاہور جا کر بیٹھ گئیں کہ بیٹے کو گھر واپس لے کر جائوں گی باپ جو فوجی افسر رہے تھے میجر راجہ دولت زر ایک دبنگ آفیسر شاہی قلعہ کا انچارج برگیڈئیر رشید قریشی ان کا شاگرد تھا نا ممکن کو بھی ممکن بنا یا اور کئی ماہ تک شاہی قلعہ میں رہنے کے بعد بالآخر رہائی کروا کر چھوڑی ورنہ عمر قید کی سزا مقدر تھی ۔ہمیشہ ثابت قدم بابائے سوشلزم شیخ رشید مرحوم مفرور ہوئے۔ پاکستان بھر کی پولیس ایجنسیاں ان کے پیچھے راجہ طاہر نے اپنے دروازے کھولے اور کئی ماہ تک اپنا مہمان بنائے رکھا ۔راجہ طاہر اپنی ذات میں پاکستان پیپلز پارٹی کی ایک تحریک اپنوں کو سوگوار چھوڑ کر چلا گیا ۔راجہ طاہر ہم تمہیں کبھی نہیں بھول پائیں گے ۔تم ہمیشہ ہمارے دلوں میں زندہ...

IMPLEMENTASI METODE ROTE LEARNING DALAM PEMBELAJARAN ILMU TAJWID

The present study aimed at finding out the portrayal of rote learning method implementation which was applied by the coaches of TPQ al-Barokah in Kampung Melayu Village, Rejang Lebong, Bengkulu. This study used a qualitative approach. The data were gathered by means of observation and interview techniques. After the data were collected, the data were analyzed using phases referring to Miles, Huberman, and Saldana comprising data condensation, data display, and drawing conclusion. The findings of this study concluded that the rote learning method for Tajwid learning was considered very effective to be applied, and its merit was evident in students’ competence in the recitation of Qur’an at TPQ al-Barokah. Their competence was seen when they were re-examined by their Qur’anic coaches, and they could provide examples of Tajwid’s application in the Qur-an properly and correctly.      

Next Generation Energy Efficient Process Protocols in Si-Cmos Electronics

As Silicon CMOS manufacturing industry is possibly reaching to its climax with complex requirements posed by the International Technology Roadmap of Semiconductors; a “More Moore” approach is fully utilized to further exploit the Silicon Fabrication protocols. This goes hand in hand with other two process and design strategies, namely, “More than Moore” and “Beyond CMOS”. A 10 node technology, converging the chip fabrication processes between 10nm and 20nm, has been rigorously tested and revisited to look for complimentary solutions which are exploitable in variety of designs and processes in next generation technology nodes. The operational output characteristics of MOS/CMOS and its variant devices are being reassessed with a perspective of energy efficiency gained during the device design (inclusive of scaling requirements) and process development. This, in turn, influences the power consumption, proficiency of performance and reliability of the devices. Such energy efficient electronics has gained a huge interest due the evolution of Internet of Things (IoT) and its ultra-low power considerations. This study focuses on the energy efficient design and fabrication of Silicon CMOS/MOSCAP devices with a detailed electrical and electro-optical metrology. A FAB-specific MOSFET design (technology file), simulated output characteristics, half-of-FAB line processing of MOSCAP structure with integration of novel Atomic Layer Deposited TiN/HfSiOx metal gate/High-k stack and atomistic-layered PVD-driven Aluminium back-contact metallization is realized in this work. Energy efficiency is also studied through the concept of thermal budget by virtue of the dynamics of annealing which greatly influence the electrical properties of the gate stack and consequently the reliability of the process. Subsequent process characterization is performed using Current-Voltage, Capacitance-Voltage, Current Density, Leakage Resistance, Built-in Voltage, Doping Profiling, Charge-storage/ Permittivity, Hall Effect and Vertical Field analysis. Sophisticated metrology techniques such as Charge-Deep Level Transient Spectroscopy and Spectroscopic Ellipsometry are utilized to extract and evaluate the hypersensitive electrical and electro-optical parameters such as charge-transient behavior, activation energy, trap density, capture cross-section, refractive index, dielectric and extinction coefficients etc. Design verification through FAB-line processing, post-FAB thermal processing and variety of measurements revealed a number of interesting results which altogether provide a novel process window to engineer energy efficient electronics with a better trade-off. These results may have ramifications for device and process engineer.
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